1. Field of the Invention
The present invention relates to the field of semiconductor devices and a manufacturing method therefor, and, more particularly the present invention relates to a bipolar transistor design and manufacturing method.
2. Description of the Related Art
In recent years, there have been demands for further large scale integration and increased performance of LSIs. In particular there has been demand for increased performance of bipolar transistor.
The performance of a bipolar transistor can be increased by reducing base transit time through narrowing of the base width, a reduction in base resistance, and a reduction in parasitic capacitance which is represented by a base-collector capacitance. In reality, however, these parameters conflict with each other, and therefore optimization is required.
For example, the reduction in base transit time by narrowing of the base width results in an increase in intrinsic base resistance. Therefore, it is necessary to find an optimum base width.
In this regard, more detailed discussion will be made with reference to FIGS. 1A to 1C, which are sectional views of an upper portion of a silicon substrate in which emitter and base regions of a high-speed npn bipolar transistor in the related art are formed.
As shown in FIG. 1C, the bipolar transistor has a so called double polysilicon structure such that electrodes for a base 13 and an emitter 14 are formed from two polysilicon layers 3 and 11, respectively. The electrodes 3 and 11 are isolated from each polysilicon layers 3 and 11, respectively. The electrodes 3 and 11 are isolated from each other by an insulating film side wall 9 to thereby greatly reduce a base-collector capacitance.
As will be understood from the following description of the manufacturing process for a bipolar transistor, the base 13 is formed by solid-phase diffusion from the emitter electrode 11 as the diffusion source, thereby preventing channeling tail from occurring in ion implantation to reduce the base width. Additionally, as shown in FIG. 1C, a link base 7 for connecting the base 13 to the base electrode 3 is formed.
The manufacturing process for the bipolar transistor mentioned above will now be described.
Referring to FIG. 1A, an insulating film 2 having a thickness of 100 to 200 nm is formed by CVD (chemical vapor deposition) on the whole surface of a silicon wafer as a substrate 1, and is then opened at a base electrode forming portion of the bipolar transistor. Then, a p-type polysilicon film 3 having a thickness of 100 to 200 nm is formed by CVD on the whole surface of the wafer. The polysilicon film 3 functions as a base electrode. The doping of the polysilicon film 3 may be performed by ion implantation. An insulating film 4 having a thickness of 300 to 400 nm is then formed by CVD on the whole surface of the wafer.
Then, a laminated film comprised of the insulating film 4 and the polysilicon film 3 is removed at the base and emitter forming portion by a known dry etching technique to form a hole 5. An insulating film 6 having a thickness of 10 to 20 nm is formed by CVD on the whole surface of the wafer. A p-type diffused layer 7 is subsequently formed by ion implantation. The p-type diffused layer 7 functions as a link base for connecting the base electrode and a base to be formed later. The insulating film 6 having a thickness of 10 to 20 nm functions as a buffer layer for preventing channeling tail in the ion implantation for forming the link base 7.
Then, annealing 900.degree. C. for 10 to 20 min is performed to diffuse impurities from the p-type polysilicon film 3 into the substrate 1, thereby forming a p.sup.+ contact layer 8 as a graft base.
Referring next to FIG. 1B, an insulating film having a thickness of 400 to 600 nm is formed by CVD, and is then wholly etched by anisotropic etching using a known dry etching technique to thereby form a side wall 9 from this insulating film and define a hole 10. The side wall 9 performs the function of isolating the base electrode 3 from an emitter electrode 11 (see FIG. 1C) which will be formed later.
Referring next to FIG. 1C, a polysilicon film 11 having a thickness of from 100 to 200 nm is formed by CVD. The polysilicon film 11 functions as an emitter electrode. Then, p.sup.+ ions are implanted into the substrate 1 and annealing is performed to thereby form a base diffused layer 13. Then, n.sup.+ ions are implanted into the base diffused layer 13 and annealing is performed to thereby form an emitter diffused layer 14.
Although not shown, electrodes are formed by using a known wiring technique after obtaining the structure of FIG. 1C.
According to this method, the base 8 is formed by the solid-phase diffusion from the polysilicon film 3, thereby eliminating the channeling tail upon ion implantation and reducing the base width.
However, the above described method has the following disadvantages. In forming the link base 7 shown in FIG. 1A, the shallow junction of the link base 7 is necessary for high performance. This can be achieved by ion implantation with low energy or counter doping of an n-type impurity.
However, the shallow junction of the link base 7 causes an increase in base resistance. That is, when an ion implantation dose is increased to reduce a base resistance, a junction depth is increased because of channeling to invite an increase in base width, or a base Gummel number is increased to cause a reduction in current amplification factor H.sub.fe, for example. As a result, the sheet resistance of the link base 7 actually becomes higher than that of the graft base 8.
Thus, an increase in base resistance is unavoidable in improving the characteristics by a reduction in base transit time.
Further, during over etching the insulating film in the formation of the side wall 9 shown in FIG. 1B, the base layer formed in the silicon substrate is partially cut because a selection ratio of silicon/silicon dioxide is unsatisfactory in this known dry etching technique, thus causing a variation in base width.
FIGS. 2A to 2C shows a second example of the bipolar transistor in the related art, which employs a stacked structure composed of a refractory metal or its silicide (WSi.sub.x in this example) film and a polysilicon film as a base electrode for the purpose of reducing a resistance of the base electrode to thereby reduce the base resistance. In this case, however, the above problems still remain, and additionally the surface condition becomes unstable through generation of a leakage current.
A manufacturing process for the bipolar transistor having the stacked structure mentioned above will now be described with reference to FIGS. 2A to 2C.
Referring to FIG. 2A, an insulating film 22 having a thickness of from 100 to 200 nm is formed by CVD on the whole surface of a silicon wafer substrate 21, and is then opened at a base electrode forming portion-of the bipolar transistor. Then, a p-type polysilicon film 23 having a thickness of from 100 to 200 nm is formed by CVD on the whole surface of the wafer. Then, a tungsten silicide (WSi.sub.x) film 24 refractory metal or its silicide film having a thickness of from 100-200 nm is formed by CVD on the whole surface of the wafer. This laminated structure composed of the tungsten silicide film 24 and the polysilicon film 23 functions as a base electrode. The doping of the polysilicon film 23 may be performed by ion implantation. Then, an insulating film 25 having a thickness of 300 to 400 nm is formed by CVD on the whole surface of the wafer.
A laminated film composed of the insulating film 25, the tungsten silicide film 24 and the polysilicon film 23 is then removed at the base and emitter forming portion by a known dry etching technique to form a hole 27. An insulating film 26 having a thickness of from 10 to 20 nm is formed on the whole surface of the wafer by CVD at a low temperature of about 400.degree. C. Then, a p-type diffused layer 28 is formed by ion implantation. The p-type diffused layer 28 functions as a base. The insulating film 26 having the thickness of from 10 to 20 nm functions as a buffer layer for preventing channeling tail in ion implantation for forming the base 28.
Referring next to FIG. 2B, an insulating film having a thickness of from 400 to 600 nm is formed by CVD, and is then wholly etched by anisotropic etching using a known dry etching technique to thereby form a side wall 30 from this insulating film and define a hole 31. The side wall 30 isolates the base electrode from an emitter electrode which will be formed later.
Referring next to FIG. 2C, a polysilicon film 32 having a thickness of from 100 to 200 nm is formed by CVD. The polysilicon film 32 functions as an emitter electrode. Then, n.sup.+ ions are implanted into the base diffused layer 28 and annealing is performed to form an emitter diffused layer 33.
Although not shown, electrodes are formed by using a known wiring technique after obtaining the structure of FIG. 2C.
As mentioned above, the CVD film 26 is formed at a low temperature of about 400.degree. C. to prevent channeling tail upon base ion implantation and also to prevent the occurrence of metal contamination due to the exposure of the tungsten silicide film 24 to the side surface of the hole 27 and the of peeling of the tungsten silicide film 24 due to stress generated in it during heat treatment. However, the low-temperature CVD film 26 is weaker in quality than an oxide film formed from the silicon substrate 21 by oxidation or a film formed by CVD at a high temperature of 700.degree. to 800.degree. C. Additionally, an interface level is generated at the interface between the silicon substrate 21 and the CVD film 26, causing instability of transistor operation. In particular, when the surface of the silicon substrate 21 is-inverted by the interface level, a collector-emitter leakage current is generated which causes a reduction in yield.
Further, the above laminated structure has the following problem. Since the diffusion coefficient of an impurity in a silicide film such as a tungsten silicide film is large, it results in the absorption of the impurity by the silicide film when using the silicide film as a drawing electrode. In the example shown in FIGS. 2A to 2C, the absorption of a p-type impurity (e.g., boron) by the silicide film 24 occurs in the base drawing electrode. More specifically, the p-type impurity in the p-type polysilicon film 23 is diffused into the tungsten silicide film 24 to segregate at the interface between the insulating film 25 and the tungsten silicide film 24. As a result, the concentration of the p-type impurity in the polysilicon film 23 and at the interface between the tungsten silicide film 24 and the polysilicon film 23 is reduced. Accordingly, the resistance of the polysilicon film 23 and the connection resistance at the interface between the tungsten silicide film 24 and the polysilicon film 23 are increased to cause an increase in external base resistance.
This problem is contrary to the original reasons for employing the silicide film for the reduction in base resistance, and it is therefore desired to solve this problem.
A recent very high-speed bipolar transistor design, has adopted a double polysilicon structure where two polysilicon films are used as emitter and base drawing electrodes. The polysilicon film which is used as the base drawing electrode has also recently been replaced by a polycide film for the purpose of reducing the base spreading resistance Rbb' to thereby further increase operating speed. As a material for forming such a polycide film, tungsten silicide is desirably used from the viewpoint of process consistency or application to a BiCMOS device, because the tungsten silicide has been established as a gate material in MOS devices.
However, in a base polycide film having a stacked structure composed of a p.sup.+ polysilicon film and a tungsten silicide film, an impurity such as boron in the p.sup.+ polysilicon film is absorbed into the tungsten silicide film which results in a reduction of the concentration of the impurity in the polysilicon film, and the diffusion of the impurity from the p.sup.+ polysilicon film into a silicon substrate is accordingly suppressed to cause an increase in contact resistance between the polysilicon film and the silicon substrate. Thus, the base spreading resistance Rbb' cannot be greatly reduced in spite of the use of the polycide film.
In this regard, more detailed discussion will be made with reference to FIGS. 3A to 3D, which are sectional views of an upper portion of a silicon substrate in which emitter and base regions of an npn bipolar transistor in the related art are formed. The bipolar transistor has a stacked structure of a p-polysilicon film and a tungsten silicide film as a base drawing electrode.
Referring to FIG. 3A, a silicon dioxide film 42 as an insulating film having a thickness of 100 nm is formed by CVD on the whole surface of a silicon substrate 41, and is then opened at a base electrode forming portion. Then, a polysilicon film 43 having a thickness of 100 nm is formed by CVD on the whole surface of the substrate 41, and a tungsten silicide film 44 having a thickness of 80 nm is then formed by CVD on the whole surface of the substrate 41. Then, boron fluoride ions (BF.sub.2.sup.+) are implanted into the polysilicon film 43 under the conditions of 30 keV and 5E15 cm.sup.-2 to form a p-type polycide film. Then, a silicon dioxide film 45 having a thickness of 300 nm is formed by CVD on the whole surface of the substrate 41. A laminated structure of the silicon dioxide film 45, the tungsten silicide film 44 and the polysilicon film 43 at a base/emitter forming portion is removed by RIE (reactive ion etching) to form a hole 52.
Then, boron fluoride ions are implanted into the substrate 41 to form a p-type diffused layer 47 (link base layer) for connecting a base electrode to a base which will be formed later. Then, annealing at 900.degree. C. for 20 min is performed to diffuse the boron ions from the p.sup.+ polysilicon film 43 into the substrate 41 to form a graft base layer 46.
Referring next to FIG. 3B, a silicon dioxide film having a thickness of 600 nm is formed by CVD on the whole surface of the substrate 41, and is then wholly etched by RIE to thereby form an emitter/base isolating side wall 50 from this insulating film and define a hole 53. Then, the silicon substrate 41 exposed to the hole 53 is etched to partially remove the link base layer 47.
Referring next to FIG. 3C, a polysilicon film 48 having a thickness of 150 nm is formed by CVD. Then, p.sup.+ ions are implanted into the substrate 41 and annealing is performed to form a base diffused layer 51. Then, n.sup.+ ions are implanted into the base diffused layer 51 and annealing is performed to form an emitter diffused layer 49.
Although not shown, electrodes are formed by using a known wiring technique after obtaining the structure of FIG. 3C. The bipolar transistor having the above-mentioned structure has the following problem.
FIG. 3D is an enlarged view of a contact portion between the base drawing electrode and the silicon substrate. In FIG. 3D, arrows show a primary route of a base current. The base current flowing in the tungsten silicide film 44 is introduced through the contact between the p.sup.+ polysilicon film 43 and the silicon substrate 41 into the graft base layer 46.
However, the boron in the p.sup.+ polysilicon film 43 is absorbed by the tungsten silicide film 44 to result in a reduction in boron concentration in the p.sup.+ polysilicon film 43. Accordingly, the contact resistance between the Polysilicon film 43 and the silicon substrate 41 is increased to generate a large series resistance. Finally, the base resistance is increased to hinder a high-speed operation.
Further, the above method involves the following problem. That is, in forming the base drawing electrode, it is necessary to align the window of the insulating film 42 and the base drawing electrode composed of the tungsten silicide film 44 and the polysilicon film 43. Accordingly, an aligning margin causes an increase in contact area, resulting in an increase in base resistance and base-collector capacitance which degrades the improvement in characteristics.
One method of solving this problem, is known in which a base electrode is formed on an insulating film and is connected through a side wall of polysilicon or the like to a silicon substrate. However, in forming the polysilicon side wall, a refractory metal or its silicide film such as a tungsten silicide film is exposed to the side surface of the hole, so that metal contamination may occur or peeling of the refractory metal or its silicide film may occur because of a stress generated therein during heat treatment.
In such a structure where the polysilicon side wall is used as a base drawing electrode, the surface of the polysilicon side wall is oxidized in order to ensure a withstand voltage of an emitter/base isolating side wall insulating film. Accordingly, the heat treatment in this oxidation similarly causes peeling of the refractory metal or its silicide film.
In association with a reduction in emitter width by a decrease in element size, the area of a diffused layer (graft base) region for base electrode drawing and the area of a link base region for connecting an intrinsic base region to the graft base region become larger than the intrinsic base region. Accordingly, a reduction in such parasitic capacitance component is essential for an increase in operating speed. On the other hand, a reduction in width of the link base region causes a deterioration in emitter-base characteristic and high-frequency characteristic in the transistor. Further, a reduction in width of the graft base region causes a problem in an aspect of process stability. Thus, it is necessary to find out an optimum point in the reduction in widths of the link base region and the graft base region.
This problem will now be further discussed with reference to FIG. 4, which is a sectional view of an upper portion of a silicon substrate 71 in which an emitter 80 and a base 78 of a high-speed npn bipolar transistor in the related art are formed. This bipolar transistor has a so-called double polysilicon structure such that an emitter electrode and a base electrode are formed from two polysilicon-films 79 and 76, respectively. The emitter electrode 79 and the base electrode 76 are isolated from each other by an insulating film side wall 81 to thereby greatly reduce a base-collector capacitance. Further, a link base for connecting the base 78 to a graft base 77 is formed.
However, in the structure shown in FIG. 4, the width of the emitter 80 is 300 nm and the width of the graft base 77 is 400 nm in design pattern, which is increased to 1100 nm after diffusion. Thus, the area of the parasitic component is very large. Accordingly, it is necessary to sufficiently narrow the graft base region without hindering the characteristics by connection of the link base, so as to increase an operating speed.
FIG. 5 shows an example of a high-speed bipolar transistor having a double polysilicon emitter-base self-aligned structure. An emitter polysilicon film 100 is larger in width than the stacked electrode of a barrier metal layer 98 and an aluminum layer 99, and is patterned simultaneously with patterning of the stacked electrode, because a large tolerance of the emitter polysilicon film 100 on a mask can be taken.
In general, an emitter polysilicon film is etched by plasma etching or RIE in a size larger than that for the stacked electrode before forming a barrier metal layer. As shown in FIG. 6A, an edge portion of an emitter polysilicon film 111 is substantially perpendicular to a background 110 in general. However, depending upon a step form of the background 110 or an over etching quantity during etching, an edge portion of an emitter polysilicon film 112 becomes reversely tapered as shown in FIG. 6B. In forming a barrier metal/aluminum stacked film on the emitter polysilicon film 112, a coverage defect of a barrier metal layer 113 may occur at the step portion as shown in FIG. 7A. Additionally, a coverage defect of an aluminum layer 114 on the barrier metal layer 113 may occur at the step portion as shown in FIG. 7B or a void 115 may be generated in the aluminum layer 114 as shown in FIG. 7C. Moreover, these defects may cause stress migration or electromigration. In addition, as shown in FIG. 7D, the intrusion of aluminum from an aluminum layer 138 into an emitter polysilicon film 137 may occur as shown by 133, causing an emitter-base junction defect.
In general, an emitter in a bipolar transistor is formed by impurity diffusion from a polysilicon film owing to the fact that washed emitter and shallow junction can be effected and a current amplification factor H.sub.fe can be increased by the presence of a native oxide at the interface between the polysilicon film and a silicon substrate.
In increasing the operating speed of a bipolar transistor, creating a shallow junction for an emitter is an important technique. Conventionally, rapid thermal annealing using a halogen lamp is generally performed to effect the shallow junction. For example, a polysilicon film doped with arsenic at a concentration of 10.sup.20 to 10.sup.21 cm.sup.-3 is formed to have a thickness of 100 to 150 nm after forming a base, and then IRA (infrared annealing) using a halogen lamp is performed to diffuse the arsenic into a single crystal silicon substrate, thereby realizing an emitter junction depth X.sub.je of 0.1 .mu.m.
However, to further reduce the emitter junction depth X.sub.je, by means of IRA, the thickness of the polysilicon film for forming the emitter must be increased to 150 to 200 nm because the wavelength range of light from the halogen lamp is wide such as 0.2 to 6.0 .mu.m or more and the light intensity at a long wavelength with a high transmissivity is large. The increase in thickness of the polysilicon film for forming the emitter causes an increase in emitter delay time due to an increase in emitter resistance R.sub.E, thus hindering high-speed operation. Accordingly, there is a limit in realizing the shallow junction of the emitter by IRA.
As another method of rapid thermal annealing, it is known to use laser irradiation instead of the halogen lamp to effect emitter diffusion. For example, in using single pulse irradiation of an excimer laser (ELA) (e.g., XeCl: pulse width of 20 ns, wavelength of 308 nm), the absorption coefficient of silicon is large such as about 10.sup.6 cm.sup.-1, and the energy of laser light absorbed is about 90% within a depth of 20 nm from the silicon surface. Accordingly, it is possible that a polysilicon film doped with arsenic at a concentration of 10.sup.20 to 10.sup.21 cm.sup.-3 is formed to have a thickness of 30 to 50 nm after forming a base, and then ELA (excimer laser annealing) is performed to diffuse the arsenic into a single crystal silicon substrate, thereby realizing an emitter junction depth X.sub.je of about 0.05 .mu.m.
However, in performing the emitter diffusion from a polysilicon film into a single crystal silicon substrate, the following problem arises. That is, the polysilicon film formed in contact with the single crystal silicon substrate at an emitter forming portion is hardly increased in temperature because the silicon substrate has good thermal conductivity and the heat in the polysilicon film is therefore dissipated into the silicon substrate. To the contrary, the polysilicon film formed on an insulating film (silicon dioxide) at a portion other than the emitter forming portion is easily increased in temperature because the insulating film has poor thermal conductivity. For example, the thermal conductivity of silicon is 148 W/mK, and the thermal conductivity of silicon dioxide is 1.38 W/mK; thus, the former is greater than the latter by two orders of magnitude. For example, when an amount of energy of 400 mJ/cm.sup.2 is absorbed into the polysilicon film having a thickness of 50 nm, the polysilicon film at the emitter forming portion takes 17 ns until it reaches the melting point, whereas the polysilicon film on the insulating film takes only 3 ns until it reaches the melting point. This has been proved from a thermal conduction simulation.
Accordingly, if ELA is performed under the conditions fit for the formation of emitter-base junction, the polysilicon film on the insulating film is excessively increased in temperature and melts. Conversely, if ELA is performed under the conditions such that the polysilicon film on the insulating film does not melt, the polysilicon film at the emitter forming portion is not increased in temperature and consequently no emitter-base junction is formed.